3D integration key to 22nm semiconductor devices

3D IC integration techniques offer many benefits, the most notable being smaller footprint, lower power and higher bandwidth. From a cost standpoint, 3D’s biggest advantage is the ability to partition large, complex dies into smaller functional blocks. This improves yield and manufacturing cost equations, and enables testing/replacement of semiconductor dies prior to integration. Furthermore, individual functional blocks enable a modular design with standardized components, e.g., an ASIC manufacturer can focus on developing the ASIC and combine it with off-the-shelf memory. This allows significant reductions in complexity and cost for design and test.

All of these benefits can be fully combined with aggressively scaled devices down to the 22nm node. Recent announcements, such as Intel’s development of a 22nm trigate transistor, underscore the fact that 22nm technology development is well under way, with volume manufacturing the next hurdle to be cleared. There has been much debate over what techniques will be implemented, in both the near and long terms, to achieve large-scale manufacture of devices at this advanced generation.

Our view is that scaling (More Moore) will continue to develop, in parallel to, although relatively independent from, 3D IC techniques. Currently implemented close to the back end of line (BEOL), 3D IC approaches, such as interposers, enable integration of dies with virtually any node. Even more forward-looking, innovative 3D IC architectures, such as wafer-to-wafer stacking, will remain largely independent from the introduction of new nodes.

In the near future, we expect to see the most complex and competitive combinations of devices being the most aggressive, both in adopting 3D integration and in heavily pushing further scaling. At the 22nm node, we also expect to see mobile, low-power and system-on-chip (SoC) applications implementing planar fully depleted silicon-on-insulator (FD SOI)-based transistors.

For many devices, implementation of the 3D system architecture alone is more attractive and cost effective. 3D ICs are already in manufacturing for niche applications like CMOS image sensors (CIS) and MEMS. It is being implemented in production for DRAM, while interposer technology is being utilized for general logic and memory integration.

The first adopters of 3D technology were MEMS, followed by analog ICs and then image sensors; CMOS foundries have built up large capacity for through-silicon via (TSV) processing and wafer-to-wafer 3D integration. We are currently at the beginning of a fourth wave of TSV and 3D adoption: high-performance logic, e.g., the Xilinx FPGA Stacked Silicon Interconnect Technology (SSIT) using a 28nm active die with a 65nm passive Interposer. We are close to adoption of 3D for stacked memory, particularly wide I/O memory-on-logic integration. Recent announcements by Micron, Samsung and Elpida are testament to the building momentum for 3D technology in high-speed, high-bandwidth memory, essential to future smartphones and tablet PCs.

In addition, IDMs, foundries and OSATs are all investing into 3D capacity. Fabless companies like Qualcomm are very actively engaged in building supply chains for 3D. JEDEC will publish the first standards in the beginning of next year. So, there is a huge and even growing market, and a rapidly developing infrastructure and supply chain.

Going forward, process integration remains a challenge in reaching time-to-market goals for 3D processes. For example, all backside processing of a thinned 50m wafer temporarily bonded to a carrier has to be qualified for various device types, which is a time-consuming proposition. In addition, process stability and yield still need to be improved for broad adoption of 3D technologies.