“The DRAM industry faces several difficult challenges today with scaling and, in particular, with lithography,” said Zvi Or-Bach, president and CEO of MonolithIC 3D, in a release. “Companies using our monolithic 3D DRAM technology can reduce their lithography risk and get a much better return-on-investment for their fab equipment.”
The monolithic 3D DRAM technology has been designed using the prevalent “ion-cut to stack high-quality single crystal silicon layers at low thermal budgets” process. Ion-cut has been employed for more than a decade in the production of silicon-on-insulator (SOI) wafers for logic technologies. The technology presents other avenues for exploitation in the form of solar usage, which is being explored by companies such as Silicon Genesis and Twin (News - Alert) Creeks Technologies.
The Monolithic 3D DRAM technology was introduced with an invited presentation at the American Vacuum Society 3D Workshop in San Jose by Dr. Deepak Sekar, chief scientist of MonolithIC 3D Inc. and presenter at the workshop. Dr. Deepak Sekar commented that “We use a 3D stacked architecture and share lithography steps among multiple memory layers. The NAND flash memory industry has been pursuing 3D technology with shared lithography steps with polysilicon transistors for some time now. At MonolithIC 3D Inc., we use single crystal silicon transistors, and that allowed us to apply these concepts to DRAM.”
The company introduced its logic technologies at the recently conducted CMOS Emerging Technologies Workshop at Whistler, Canada and at a 3D workshop held at the International Conference on Technology & Instrumentation in Particle Physics in Chicago.
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