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2011年5月8日星期日

Intel finds higher speed in new dimension

The transistors on computer chips – whether for PCs or smartphones – have been designed in essentially the same way since 1959 when Intel co-founder Robert Noyce and Texas Instruments’ Jack Kilby independently invented the first integrated circuits that became the basic building block of electronic devices in the information age.

These early chips were built on a flat surface. But like a real estate developer building skyscrapers to get more rentable space from a plot of land, Intel is now building up. When the space between the billions of tiny electronic switches on the flat surface of a computer chip is measured in the width of just dozens of atoms, designers needed the third dimension to find more room.

The company has already begun making its microprocessors using a new 3D transistor design, called a Finfet (for fin field-effect transistor), which is based around a remarkably small pillar, or fin, of silicon that rises above the surface of the chip. Santa Clara, California-based Intel plans to enter general production based on the new technology some time later this year.

Although the company did not give technical details about its new process, it said that it expected to be able to make chips that run as much as 37 percent faster in low-voltage applications and it would be able to cut power consumption as much as 50 per cent. Intel currently uses a photolithographic process to make a chip, in which the smallest feature on the chip is just 32 nanometres, a level of microscopic manufacture that was reached in 2009. (By comparison a human red blood cell is 7,500 nanometres in width and a strand of DNA is 2.5 nanometres.) “Intel is on track for 22-nanometer manufacturing later this year,” said Intel senior fellow and scientist Mark T Bohr, who has overseen the effort to develop the next generation of smaller transistors.

The company’s engineers said that they now felt confident that they would be able to solve the challenges of making chips through at least the 10-nanometre generation, which is likely to happen in 2015.

The timing of the announcement is significant, Bohr said, because it is evidence that the world’s largest chip-maker is not slipping from the pace of doubling the number of transistors that can be etched onto a sliver of silicon every two years, a phenomenon known as Moore’s Law.

Although not a law of physics, the 1965 observation by Intel co-founder Gordon Moore, has defined the speed of innovation for much of the world’s economy. It has also set the computing industry apart from other types of manufacturing because it has continued to improve at an accelerating rate, offering greater computing power and lower cost at regular intervals.

However, despite its promise and the company’s bold claims, Intel’s 3D transistor is still a controversial technology within the chip industry. Indeed, a number of the company’s competitors say they believe that Intel is taking what could be a disastrous multibillion-dollar gamble on an unproved technology. There has been industry speculation that Finfet technology will give Intel a clear speed advantage, but possibly less control over power consumption than alternative approaches. By opting for a technology that emphasises speed over low power, Intel faces the possibility that it could win the technology battle and yet lose the more important battle in the marketplace.

The scope of Intel’s gamble is underscored by the fact that while the company dominates in the markets for data centre computers, desktops and laptops, it has largely been locked out of the tablet and smartphone markets, which are growing far more quickly than the traditional PC industry. Those devices use ultra-low-powered chips to conserve battery power and reduce overheating.

Apple, for example, uses Intel microprocessors for its desktops and laptops, but for the iPhone and iPad it has chosen to use a rival low-power design, built by others, that Apple originally helped pioneer in the late 1980s.
Industry executives and analysts have said that Intel is likely to have a lead of a full generation over its rivals in the shift to 3D transistors. For example, taiwan-based chip-maker TSMC has said that it does not plan to deploy Finfet transistor technology for another two years.

Other companies, like ST Microelectronics, are wagering that an alternative technology based on placing a remarkably thin insulating layer below traditional transistors will chart a safer course toward the next generation of chip manufacturing. They believe that the insulation approach will excel in low-power applications, and that could be a crucial advantage in consumer-oriented markets where a vast majority of popular products are both hand-held and battery-powered.

“Silicon-on-insulator could be a win in terms of power efficiency,” Semiconductor Manufacturing and Design Community website editor-in-chief David Lammers said. “From what I am hearing from the SOI camp, there is a consensus and concession that Finfets are faster. That’s the way you want to go for leading-edge performance.”

In a factory tour here last week, Intel used a scanning electronic microscope to display a computer chip made using the new 22-nanometre manufacturing process. Viewed at a magnification of more than 1,00,000 times, the silicon fins are clearly visible as a series of walls projected above a flat surface. It is possible to make transistors out of one or a number of the tiny fins to build switches that have different characteristics, such as faster switching speeds or extremely low power. Looking at the chip under less magnification, it is possible to see the wiring design, which appears much like a street map displaying millions of intersections.

Despite the impressive display, Intel’s executives acknowledge the challenge the company is facing in trying to catch up in the new consumer markets that so far have eluded it.

“The ecosystem right now is not aligned in our favor,” said Intel chief administrative officer Andy D Bryant, who now runs the company’s technology and manufacturing group. “It has to be good enough for the ecosystem to take notice and say, ‘We better pay attention to those guys.”

2011年5月2日星期一

The theory of Wan et al

Topology, the mathematical description of the robustness of form, appears throughout physics, and provides strong constraints on many physical systems. It has long been known that it plays a key role in understanding the exotic phenomena of the quantum Hall effect. Recently, it has been found to generate robust and interesting bulk and surface phenomena in “ordinary” band insulators described by the old Bloch theory of solids. Such “topological insulators,” insulating in the bulk and metallic on the surface, occur in the presence of strong spin-orbit coupling in certain crystals, with unbroken time-reversal symmetry [1].

It is usually believed that such topological physics is obliterated in materials where magnetic ordering breaks time-reversal symmetry. This is by far the most common fate for transition-metal compounds that manage to be insulators—so called “Mott insulators,” which owe their lack of conduction to the strong Coulomb repulsion between electrons. In an article appearing in Physical Review B, Xiangang Wan from Nanjing University, China, and collaborators from the University of California and the Lawrence Berkeley National Laboratory, US, show that this is not necessarily the case, and describe a remarkable electronic structure with topological aspects that is unique to such (antiferro-)magnetic materials [2]. The state they describe is remarkable in possessing interesting low-energy electron states in the bulk and at the surface, linked by topology. In contrast, topological insulators, like quantum Hall states, possess low-energy electronic states only at the surface.

The theory of Wan et al., which uses the LDA+U numerical method, is a type of mean field theory. As such, the low-energy quasiparticle excitations are described simply by noninteracting electrons in a background electrostatic potential and, in the case of a magnetically ordered phase, by a spatially periodic exchange field. It is possible to follow the evolution of the electronic states as a function of the U parameter, which is used to model the strength of Coulomb correlations. They apply the technique to iridium pyrochlores, R2Ir2O7, where R is a rare earth element. These materials are known to exhibit metal-insulator transitions (see, e.g., Ref. [3]), indicating substantial correlations, and are characterized by strong spin-orbit coupling due to the heavy element Ir (iridium). In the intermediate range of U, which they suggest is relevant for these compounds, Wan et al. find an antiferromagnetic ground state with the band structure of a “zero-gap semimetal,” in which the conduction and valence bands “kiss” at a discrete number (24!) of momenta. The dispersion of the bands approaching each touching point is linear, reminiscent of massless Dirac fermions such as those observed in graphene.

This would be interesting in itself, but there are important differences from graphene. Because of the antiferromagnetism, time-reversal symmetry is broken, and as a consequence, despite the centrosymmetric nature of the crystals in question, the bands are nondegenerate. Thus two—and only two—states are degenerate at each touching point, unlike in graphene where there are four. In fact, the kissing bands found by Wan et al. are an example of accidental degeneracy in quantum mechanics, a subject discussed in the early days of quantum theory by von Neumann and Wigner (1929), and applied to band theory by Herring (1937). The phenomenon of level repulsion in quantum mechanics tends to prevent such band crossings. To force two levels to be degenerate, one must consider the 2×2 Hamiltonian matrix projected into this subspace: not only must the two diagonal elements be made equal, the two off-diagonal elements must be made to vanish. This requires three real parameters to be tuned to achieve degeneracy. Thus, without additional symmetry constraints, such accidental degeneracies are vanishingly improbable in one and two dimensions, but can occur as isolated points in momentum space in three dimensions (the three components of the momentum serving as tuning parameters). An accidental touching of this type is called a diabolical point. The 2×2 matrix Schrödinger equation in the vicinity of this point is mathematically similar to a two-component Dirac-like one, known as the Weyl equation. Thus the low-energy electrons in this state behave like Weyl fermions. A property of such a diabolical point is that it cannot be removed by any small perturbation, but may only disappear by annihilation with another diabolical point.